The invention relates to methods for reducing bus latency in a computer system and, in particular, to such methods in computers including a data bus controller.
The typical computer system communicates almost continuously with peripheral devices attached to the system. This creates a requirement for high performance, bidirectional data transmission to accomplish mass information transfer. One way this requirement is met is through the use of a high speed serial data bus to which the peripheral devices are interfaced through one or more bus controller devices.
A primary aspect of the information transfer when communicating with a peripheral device is reading from and writing to the memory of the computer system by accessing the system""s peripheral device access bus, for example by accessing a peripheral component interconnect (PCI) data bus. This is accomplished by performing direct memory access (DMA) through use of a DMA controller which oversees the system memory read and write functions for peripheral data independent of the central processor unit (CPU). Use of a DMA controller provides a more efficient way in which to perform memory read and write tasks related to peripherals than by using the CPU to do so. This is due to the capability of the DMA controller to transfer large blocks of data at one time, whereas the CPU is limited to a register-by-register procedure.
The DMA controller communicates with the CPU to acquire control of the system memory bus for a memory read or write task, and then signals the CPU when the task is complete. The DMA controller returns control of the system memory bus to the CPU only when it determines that the data transfer is completed. The CPU is idle during the time required for the data transfer since two devices cannot access the memory bus simultaneously, and the serial data bus is unavailable for use by any other attached peripheral device while a data transfer is taking place. The availability of the system memory bus and serial data bus determine the computer system""s bus latency or dormancy, which directly influences the overall system performance as related to CPU idle time.
Typically, a data bus controller contains memory devices for temporarily storing the data to be transferred, and no data is stored in the DMA controller. The number and size of these memory devices and their utilization scheme largely determine the efficiency with which the bus controller is able to effect a data transfer.
FIG. 1 shows an IEEE Standard 1394 high speed serial data bus controller, 1394 Bus Controller 1, and the data path to an IEEE Standard 1394 physical layer device, 1394 Physical Layer 6, to which Peripheral Devices 7 are connected. The 1394 Physical Layer 6 typically includes cable transceivers and arbitration logic for peripheral device interfacing.
1394 Bus Controller 1 is capable of transferring data packets between Peripheral Devices 7 and the computer system memory (not shown) by performing direct memory access. Data structures referred to as descriptors, sometimes referred to as packet control lists (PCL), completely describe the data to be transferred including sources and destinations, how many bytes of data are to be transferred, and error control information.
In the discussion that follows the transfer of data will be described in the context of data being transferred from one of the peripheral devices in Peripheral Devices 7 to computer system memory (not shown). The transfer of data from system memory to a peripheral device is similar in most respects, and in order to avoid duplicative description will therefore not be described in detail.
When the peripheral device is required to transfer data it submits a system memory read or write request to a 1394 Link Layer Control Logic unit (LLC) 5 through a 1394 Physical Layer 6. The LLC 5 directs the request to DMA Logic 3. DMA Logic 3 then acquires control of the system memory bus, placing the CPU (not shown) in an idle state. The data to be transferred is acquired by LLC 5 through 1394 Physical Layer 6 and written to first-in-first-out (FIFO) memory in FIFO Logic 4. When DMA Logic 3 determines that all criteria for the transfer have been met in accordance with the descriptors, DMA Logic 3 causes the data to be transferred from the FIFO memory to the PCI Bus through PCI Logic in a PCI and Local Bus Interface unit 2, and to be written to system memory. Upon completion of the memory write cycle LLC 5 signals the peripheral device that the transfer is complete, at which time the device must return an acknowledgment to LLC 5 in order to close out the transfer. The CPU is then signaled by DMA Logic 3 that the transfer is complete, at which time the CPU acquires control of the system memory bus and resumes processing.
If for any reason the peripheral device does not issue the required acknowledgment, as might be the case if the device were busy, LLC 5 can not close out the transfer and release the system memory bus. The device may also request a retry of the data transfer, which is sometimes done to provide more current data, which too prevents release of the memory bus back to the CPU.
Computer systems typically include provisions for limiting the time the bus controller must wait for device acknowledgment and the maximum number of transfer retries permitted for purposes of overall system performance. These limits are usually not so stringent, however, as to prevent unacceptable bus latency.
In accordance with the present invention there is provided a serial bus controller having improved bus performance when a physical read request or a physical write request is present. A link and physical layer logic unit is provided, coupled to a serial bus having at least one peripheral device coupled thereto. A host interface is provided, coupled to a host data bus. A request FIFO is provided, coupled to receive a host memory read or write request packet from the link and physical layer logic unit, and coupled to said host interface. A physical read request FIFO is provided, coupled to receive a physical read request from the request FIFO for further processing of the physical read request. A physical write request FIFO is provided, coupled to receive a physical write response for transfer to the peripheral device.